The present invention relates to an electrically erasable nonvolatile memory, or an EEPROM, having semiconductor memory cells including selecting MIS transistors, storage MIS transistors, control MIS transistors, word lines, control lines, and bit lines.
Referring to FIG. 5, a conventional EEPROM has memory cells 48 in which selected word line 40 and control line 41 are set high (20 V) during erasure. At the same time, a control gate 46 selected by these lines is set high. During writing, selected word line 40 and bit line 42 are set high. At the same time, the drain 47 of a storage MIS transistor 45 selected by them is set high. When the erasure or the writing ends, the supply of the high voltage is stopped. When the erasure ends, the source of the high voltage is kept at ground level (0 V) for a given time (several microseconds) while maintaining the control line 41 and the control gate 46 in selected state. When the writing ends, the source of the high voltage is kept at ground level for a given time while maintaining the bit line 42 and the drain 47 of the storage MIS transistor 45 in selected state. In this way, when the erasure ends, the selected control line 41 and control gate 46 are electrically discharged. When the writing ends, the selected bit line 42 and the drain 47 of the storage MIS transistor 45 are electrically discharged.
Referring to FIG. 6, a timer circuit 85 has a clock-generating circuit 49 to which a program-interrupting signal 56 is coupled. The clock-generating circuit 49 is connected with a counter circuit 50, which is in turn connected with a decoder circuit 51. A word line driver 52, a control line driver 53, and a bit line driver 54 are connected with the timer circuit 85 and also with memory cells 55. The aforementioned program-interrupting signal 56 is also coupled to the memory cells 55. This timer circuit controls the potentials at the word line 40, the control line 41, and the bit line 42.
In the conventional EEPROM, if the program is interrupted during erasure or writing, the word lines selected immediately before the interruption of the program drop to ground level. The control lines or bit lines selected immediately before interruption of the program are released, i.e., have high impedance. Therefore, electric charge remains either on the control lines and the control gates or on the bit lines and the drains of the storage MIS transistors due to the high voltage. As a result, erroneous erasure, erroneous writing, and erroneous reading take place. Accordingly, the present invention is intended to solve this problem with the prior art techniques. It is an object of the present invention to provide an EEPROM which electrically discharges electric charge due to high voltage on a memory array by shortening a program timing pulse when the program is interrupted during erasure or writing and ending the program with a short cycle, whereby preventing erroneous erasure, erroneous writing, and erroneous reading.